Synthesizing FPGA Circuits from Parallel Programs

From silicon to science : the long road to production reconfigurable supercomputing p. 2 The von Neumann syndrome and the CS education dilemma p. 3 Optimal unroll factor for reconfigurable architectures p. 4 Programming reconfigurable decoupled application control accelerator for mobile systems p. 15 DNA physical mapping on a reconfigurable platform p. 27 Hardware BLAST algorithms with multi-seeds detection and parallel extension p. 39 Highly space efficient counters for Perl compatible regular expressions in FPGAs p. 51 A custom processor for a TDMA solver in a CFD application p. 63 A high throughput FPGA-based floating point conjugate gradient implementation p. 75 Physical design of FPGA interconnect to prevent information leakage p. 87 Symmetric multiprocessor design for hybrid CPU/FPGA SoCs p. 99 Run-time adaptable architectures for heterogeneous behavior embedded systems p. 111 FPGA-based real-time super-resolution on an adaptive image sensor p. 125 A parallel hardware architecture for image feature detection p. 137 Reconfigurable HW/SW architecture of a real-time driver assistance system p. 149 A new self-managing hardware design approach for FPGA-based reconfigurable systems p. 160 A preemption algorithm for a multitasking environment on dynamically reconfigurable processor p. 172 Accelerating speculative execution in high-level synthesis with cancel tokens p. 185 ARISE machines : extending processors with hybrid accelerators p. 196 The instruction-set extension problem : a survey p. 209 An FPGA run-time parameterisable log-normal random number generator p. 221 Multivariate Gaussian random number generator targeting specific resource utilization in an FPGA p. 233 Exploring reconfigurable architectures for binomial-tree pricing models p. 245 Hybrid-mode floating-point FPGA CORDIC co-processor p. 256 Multiplier-based double precision floating point divider according to the IEEE-754 standard p. 262 Creating the world's largest reconfigurable supercomputing system based on the scalable SGI Altix 4700 system infrastructure and benchmarking life-science applications p. 268 Highly efficient structure of 64-bit exponential function implemented in FPGAs p. 274 A framework for the automatic generation of instruction-set extensions for reconfigurable architectures p. 280 PARO : synthesis of hardware accelerators for multi-dimensional dataflow-intensive applications p. 287 Stream transfer balancing scheme utilizing multi-path routing in networks on chip p. 294 Efficiency of dynamic reconfigurable datapath extensions-a case study p. 300 Online hardware task scheduling and placement algorithm on partially reconfigurable devices p. 306